Factors That Increase PCB Cost

Panel Material Utilization is the most important factor affecting PCB cost

PCB producers manufacture panels, not individual PCBs. Manufacturing panels come in various sizes. Some are optimized for special process or materials, others are optimized for high-volume PCB production, and many panel sizes are manufacturer-specific. Panel utilization must be considered in the very early phases of product design, not at PCB layout, since product attributes often dictate form factor and circuit size. When calculating units per production panel, include waste tabs/keep-outs required for PCB assembly.

IPC6012 Class 2 vs. Class 3 = 10-20% cost adder

IPC Class 2 requires cross-sections to be done on a sampling basis per customer requirement, if any. Most customers do not request sections.

IPC Class 3 requires cross-sections to be done on 100% of the manufacturing panels. PCB cost impact is as follows:

1. Greatly increased lab time for sectioning and report creation due to lower C=0 Sampling index.
2. Coupons must be removed, documented, and retained.
3. Additional coupons are required for Class 3 product versus Class 2, due to sectioning and retention requirements. PCB number up and panelization can be affected.

IPC Class 3 requirements result in some special process steps that consume production time and resources:

Attributes	IPC 6012 Class 2	IPC 6012 Class 3	IPC 6012 Class 3A
Annular Ring:  Extrnal  Internal	90° breakout acceptable 90° breakout acceptable	2mil min 1mil min	2mil min 2mil min
Bow & Trist	0.75% max, if SMT used 1.5% max, for other	0.75% max, if SMT used 1.5% max, for other	if not specified 3.5mil 2plys min min 1mil (25um)
Dielectric Thickness	If not specified, 3.5mil min 1mil (25um)	If not specified, 3.5mil min 1mil (25um)	if not specified 3.5mil 2plys min min 1mil (25um)
Cu Plating	Elongation 12% min; Tensile strength 36,000 psi min	Elongation 12% min; Tensile strength 36,000 psi min	Elongation 18% min; Tensile strength 40,000 psi min
Through Holes	avg 7.87mil (20um) min 7.09mil (18um)	avg 9.84mil (25um) avg 7.87mil (20um)	avg 1.5mil (38um) min 1.2mil (30um)
Blind Vias	avg 7.87mil (20um) min 7.09mil (18um)	avg 9.84mil (25um) avg 7.87mil (20um)	avg 1.5mil (38um) min 1.2mil (30um)
Buried Vias	avg 7.87mil (20um) min 7.09mil (18um)	avg 9.84mil (25um) avg 7.87mil (20um)	avg 1.5mil (38um) min 1.2mil (30um)
Microvias	avg 0.472mil (12um) min 0.394mil (10um)	avg 0.472mil (12um) min 0.394mil (10um)	avg 0.8mil (20um) –
Conductor Width Reduction	not >20% of min	not >20% of min	not >20% of min
Etchback	when specified 0.2mil-0.3mil	when specified 0.2mil-0.3mil	0.2mil-0.15mil when requried
Negative Etchback	shall not exceed 1mil	shall not exceed 0.5mil	not acceptable
Crazing	shall not span more than 50% of the distance between conductors	shall not span more than 50% of the distance between conductors	no crazing allowed
Delamination /Blistering	shall not span more than 50% of the distance between conductors	shall not span more than 50% of the distance between conductors	no delamination allowed no blistering allowed
Nailheading	Accetable	Accetable	Accetable

1. All panels are serialized to ensure full traceability
2. Plating times are 25% longer (1mil min vs. 0.8mil min)
3. Additional in-process micro-sectioning is completed in order to ensure compliance with Class 3 requirements for copper and annular ring.
4. Aside from the section and reporting requirements, what are the two main design differences between Class 2 and Class 3 PCBs? Annular Ring requirements (internal and external) -Require design modification. Plating Thickness requirements -Mainly a process modification for the PCB Manufacturer.
5. The cost of going to Class 3 is primarily in the reporting and sectioning requirements of the spec, as well as the lost space in panelization due to additional coupon placement.
6. If Class 3 product performance without the cost is desired design with Class 3 annular ring and require extra plating, but specify Class 2 performance. Eliminate extra coupon requirements and subsequent lost space on the panel.
7. High-reliability PCB Manufacturers usually have one main process flow, which is already set-up for Class 3 performance, for process simplification.

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Layer Count

1. Every two layers (core) added to multi-layer Printed Circuit Board (PCB) will add 20% -25% to the unit cost.
2. Odd layers do not save money. For example, a 9 layer PCB costs the same as an 10 layer PCB, due to the standard manufacturing processes involved. Standard cores are supplied to PCB producers as 2-sided (Cu foil on bot sides). Internal layers are processed in pairs (individual cores).

Fixed Costs – Line Width and Feature Spacing

1. Standard is 4mil/4mil (0.102mm) Trace width/spacing on 1/2oz material.
2. 3mil/3mil (0.076mm) Trace width/spacing adds 20%-30%
3. 2.5mil/2.5mil (0.051mm) Trace width/spacing adds 20%-30%
4. If thinner trace width and spacing are required within a confined area (BGA), using them only where needed with result in higher yields than using across the PCB.

Impedance Trace Identification Helpful Hint

Use unique ‘D-codes’ (aperture line widths) for each impedance controlled trace so that the traces can be picked out and modified independently of other lines or fills. The D-codes can be as different as 0.0001 mil. For example, use a 4.01 mil for an impedance controlled line width, and 4 mil for a non-controlled line width (or different ohm lines), or line-drawn plane fills.

Fixed Costs – Impedance Tolerance

1. +/-10% tolerance is standard
2. +/-7% tolerance adds 20%
3. +/-5% tolerance adds 30%
4. Paying for the tightened impedance tolerance may be of no benefit if the proposed stackup and material set are not robust. Standard TDR coupon per IPC-2221 requirements is used for verification. Actual PCB is more likely to have unpredictable variations than the coupon.
5. Etching tolerances are independent of trace widths, and improved tolerances can be obtained by using wider traces. A 0.1mil trace width difference on a 3mil 50ohm trace equals 1.6%. A 0.1mil trace width difference on a 5mil 50ohm trace equals 0.9%.

Impedance Variation due to Poor Copper Distribution

Thieving squares/dots or solid copper area fill eliminates poor feature distribution *Maintain 0.200” min keep-out zone from any copper feature.

Stackups – Symmetry

1. With BGA devices prevalent in today’s designs, flatness is critical.
2. Symmetry is the most important step that can be taken to ensure that no warpage or residual stresses are present in the final product.
3. The build should be symmetrical about the Z-axis, including copper, prepregs, and cores.
4. When possible, use single-ply cores, except for heavy copper designs.
5. The best builds will utilize the same core thickness and prepreg style throughout.

Variable Costs – Mechanical Drilling

1. How about the Number of Drill Sizes on a particular design?
2. This is a challenge for many Circuit Board Manufacturers, as having too many drill sizes results in more drill bits required in each “kit” for PCB manufacturing, particularly if each drill size is used for a small number of holes, and can lead to a cost adder, if excessive.
3. Finished hole sizes are drilled oversized by 4-6mil (0.1-0.15mm) by PCB Board Manufacturers in order to account for subsequent plating requirements (copper + final finish).
4. Hole diameters that are close will generally be drilled with the same size drill bit, as long as finished diameter is within specified tolerance.

Fixed Cost Adders – Board Thickness

Any thickness up to 93mils (2.4mm) is considered standard. Thin cores cost more.

1. 94-120mils (2.38-3.05mm) adds 10%-20%.
2. 121-250mils (3.07-6.35mm) adds 25%-35%
3. Design review is required for anything over 250mils (6.35mm). Equipment limitations or under 20mils (0.5mm) handling issues.

Fixed Cost Adders – Surface Finish

1. OSP, Immersion Silver, ENIG, and SnPb HASL are not adders.
2. ENEPIG adds 10% per manufacturing panel
3. Lead-Free HASL adds 5% per manufacturing panel.
4. Hard Gold is priced per sq.m area at the current market prices of gold.
5. Selective Finishes (combinations) are priced on an individual basis.

Fixed Cost Adders – Fabrication

1. Scoring -No PCB cost adder
2. Milling: 5%-10% at +/-5mil (0.127mm) tolerance
3. Edge Plating: 5%-10% plus additional PCB costs associated with reduced up on the manufacturing panel, if affected.
4. Back Drilling: 15%-25%
5. Castellations /Half Holes: 10%-15% depending on size and density.
6. Cavities: Avoid if possible! -Price is design specific.

Soldermask & Silkscreen

1. Glossy or Matte soldermask: no PCB cost adder.
2. Different Color (non-green) Soldermask: 5%-10%, depending on lot size. Use caution with Black or White soldermask (cost, capability, and yield issues). The cost adder for different soldermask is due to having to break down the set-up for one color in order to use another (time consuming, ink storage issues, etc.)
3. Soldermask is a Continuous Process, and the application is independent of the PCB design, except for 2oz copper and greater (double coat).
4. However, the Silkscreen process is a batch process, and is set-up for each particular worker order / part number. Only Printed nomenclature is cost adder, an option for greater legibility when text is smaller than standard (35mil high).
5. Customers that use different soldermask colors to identify RoHS or lead-free products should consider using a different silkscreen color instead.

Internal & External Annular Ring

1. Internal annular ring measurements DO NOT include through hole plating
2. Internal annular ring is measured from Drilled edge to etched edge of foil.
3. External annular ring measurements DO include through hole plating

HDI – Technology Adds Cost (and Time)

1. In many cases (0.5mm BGA, 0.4mm BGA, via-in-pad, reduced PCB size), the use of HDI PCB is unavoidable.
2. Blind Vias (Laser): 10%-15% per Layer (second side is 5%)
3. Buried Vias (Laser): 40%-50% (plus any sub filling costs if stacked).
4. Blind Vias (Mechanical): 50%-100% (plus any sub filling costs if stacked).
5. Through Hole Fill (non-conductive): 20% per Panel.
6. Subassembly Hole Fill (non-conductive): 15% per Layer.
7. Microvia Copper Fill: 20% per Layer.
8. Buried Capacitance: 5% per Std BC Core (more for high performance material’s).
9. Buried Resistance: 75% per Resistive Layer.
10. Adders for Hole Fill, Laser Microvias, and/or Mechanical Blind/Buried holes are for the process itself and are not dependent on the total number of holes.
11. Once you add one blind/buried/filled via, you can use as needed to take advantage of the increased density.
12. When Via Fill is considered, maintain a single hole size for optimized filling.
13. Copper filling multiple microvias on the same layer is as cost effective as filling just one microvia.

Build Complexity

1. Laser drilled microvias with internal buried vias are preferred over mechanical blind vias for ease of manufacture, especially with respect to external layer wrap plate processing.
2. When considering blind vias, the following rules of thumb will help make the design more robust:

Design the build so that the blind vias are symmetrical about the center axis and extend to the middle. Example: 12 layer PCB with blinds L1-L6 &L7-L12, instead of L1-L5 &L8-L12.

• If possible, consider PCB with back drilling on long blind vias. Example: 12 layer PCB with blinds L1-L5 (consider a straight build with back drills). And less expensive and less time consumption than nultiple lams.
• If only one set of blind vias is required, the build should be mirrored on the opposite side using a dummy subassembly and heavier copper to mimic the extra Cu plating on the blind via subassembly.

Asymmetric Subassemblies

On subassemblies where the build is unbalanced, use dummy subassemblies and copper weight changes to force the build into a more symmetric state.